Job Description:

l        Responsibility: In this position the candidate will

l        Be responsible SDH product related development, Test case development, Logic verification and assist the design team to fix bugs;

l        Develop test plan from specification;

l        Design verification infrastructure and execute exhaustive logic verification;

Job Description:

l        BSEE or MSEE or equivalent   with over 3 years experience in design verification;
Specific application areas: SDH preferred

l        Using scripting languages;(e.g. TCL, shell)

l        Experience of designing verilog/vhdl based simulation test benches;

l        Have writing PLI routines and running simulations Experience with Vera or Specman test languages;(optional)

l        Familiar with formal verification tools;(optional)

l        Familiar using programming language C++ is preferred;(optional)

l        Excellent analysis and debugging skills.

l        Good communication and interpersonal skills and team motivator and team player.