高级硬件工程师
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职位描述/要求：
资格条件：
- 电子工程学或计算机工程学的学士BS或硕士MS学位，或具备相当的工作经验
- 对基于Intel或PowerPC的硬件体系结构、相关的总线（PCI，PCI-Express，DDR2等）、和标准的接口（如SATA, SAS, Ethernet, SDH等）具有坚实的知识基础
- 具备熟练使用EDA工具的经验：Cadence Capture 或HDL, 和Allegro等。
- 在硬件工程方面, 至少需要5年研发设计R&D经验
- 在硬件工程中相关的大批量产品上，必须至少具备3年的研发设计R&D经验
- 必须具备领导硬件项目开发的实际经验
- 深度理解硬件工程流程和质量控制需要
- 具有广泛的相关高速电路设计的知识，包括数字和模拟电路的设计、DC-DC转换的设计、信号完整性的设计知识，都是非常需要的
- 具有Cadence概念的设计经验，和Allegro工具的使用经验
- 需要具备CPLD/FPGA开发的实际经验
- 需要具备比较强的英文书写，和口头交流的技能
- 具有自我激励、和创新能力，责任心强 Qualifications - BS/MS in Electrical Engineering, or Computer Engineering or equivalent work experience is required.- Solid knowledge of Intel or PowerPC hardware architecture, associated buses (PCI, PCI-Express, DDR2, etc.) and standard interfaces (SATA, SAS, Ethernet, SDH, etc.) is required.
- EDA tools experience: Cadence Capture or HDL, and Allegro etc.
- A minimum of 5 years R&D experience in hardware engineering is required.
- A minimum of 3years in R&D experience in hardware engineering associated mass products is strongly desired.
- Experience in leading hardware development in projects is strongly desired.
- Deep understanding of hardware engineering process and quality control is required.
- Extensive knowledge of associated high speed circuit design including digital and analog design, DC-DC converter, signal integrity, etc. is strongly desired.
- Design experience with Cadence concept/Allegro tools is desired.
- Experience in CPLD/FPGA development is desired.
- Strong English written and verbal communications skills are desired.
- Self-motivate, accountable, innovative.
注：条件不符者勿扰！谢谢！ 联系方式：
地址：武汉市东湖新技术开发区吴家湾联合国际大厦1003室 Email：ptseng@landmark.com.cn | |||||||||||||
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