赴新加坡半导体Tapeout - Deck Development Engineer
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职位描述/要求：
受新加坡某半导体公司委托，招聘Tapeout - Deck Development Engineer
工作地点：新加坡 Responsibilities: Support FE, TD, EDA and Fabs in pre-tapeout and tapeout phases of prototype in the area of design rule, layer generation operation and OPC. Provide technical support to Field Engineer to ensure customer requirements are implemented. Provide technical support to Module engineer/Process Integration engineer to ensure all requirements and changes are implemented. Development of Design Rule run sets. Create and update the design rule run sets. Create layout structures according to design rule for the purpose of checking the design rule run sets, co-relate DRC results across different verification tools. Feedback to EDA vendors if result is not acceptable. Ensure all run sets are verified prior to sending to customer. Feedback to process owner if errors are detected in the design rule specification Develop, implement and qualification of layer generation (Dataprep) including OPC & ORC scripts. Champion and drive continuous improvement programs and automation. Requirements: Minimum 3 years of relevant working experience. Knowledge of design rule verification tools e.g. Calibre, Assura, Dracula, Hercules. is a must. Strong analytical capability to understand business issues and analyze user requirements. Good inter-personal and communication skills are necessary. Required to identify solutions to problems with little guidance and implement them independently. Ability to interact effectively with both external and internal customers at all levels and from various cultural background. Good PSDM skill. Applicants must be willing to work in Woodlands. 联系方式：
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